? semiconductor components industries, llc, 2014 january, 2014 ? rev. 7 1 publication order number: mtb50p03hdl/d mtb50p03hdl, mvb50p03hdlt4g p-channel power mosfet 50 a, 30 v, logic level d 2 pak this power mosfet is designed to withstand high energy in the avalanche and commutation modes. the energy efficient design also offers a drain ? to ? source diode with a fast recovery time. designed for low voltage, high speed switching applications in power supplies, converters and pwm motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. features ? avalanche energy specified ? source ? to ? drain diode recovery t ime comparable to a discrete fast recovery diode ? diode is characterized for use in bridge circuits ? i dss and v ds(on) specified at elevated temperature ? short heatsink tab manufactured ? not sheared ? specially designed leadframe for maximum power dissipation ? mvb prefix for automotive and other applications requiring unique site and control change requirements; aec ? q101 qualified and ppap capable ? these devices are pb ? free and are rohs compliant maximum ratings (t c = 25 c unless otherwise noted) rating symbol value unit drain ? source voltage v dss 30 vdc drain ? gate voltage (r gs = 1.0 m ) v dgr 30 vdc gate ? source voltage ? continuous ? non ? repetitive (t p 10 ms) v gs v gsm 15 20 vdc vpk drain current ? continuous drain current ? continuous @ 100 c drain current ? single pulse (t p 10 s) i d i d i dm 50 31 150 adc apk total power dissipation derate above 25 c total power dissipation @ t c = 25 c, when mounted with min. recommended pad size p d 125 1.0 2.5 w w/ c w operating and storage temperature range t j , t stg ? 55 to 150 c single pulse drain ? to ? source avalanche energy ? starting t j = 25 c (v dd = 25 vdc, v gs = 5.0 vdc, peak i l = 50 apk, l = 1.0 mh, r g = 25 ) e as 1250 mj thermal resistance ? junction ? to ? case ? junction ? to ? ambient ? junction ? to ? ambient, when mounted with the minimum recommended pad size r jc r ja r ja 1.0 62.5 50 c/w maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. d s g marking diagram & pin assignment mtb 50p03hg ayww 1 gate 4 drain 2 drain 3 source 50 amperes 30 volts r ds(on) = 25 m d 2 pak case 418b style 2 1 2 3 4 p ? channel mtb50p03h = device code a = assembly location y = year ww = work week g = pb ? free package http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. ordering information
mtb50p03hdl, mvb50p03hdlt4g http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drain ? to ? source breakdown voltage (c pk 2.0) (note 3) (v gs = 0 vdc, i d = 250 adc) temperature coefficient (positive) v (br)dss 30 ? ? 26 ? ? vdc mv/ c zero gate voltage drain current (v ds = 30 vdc, v gs = 0 vdc) (v ds = 30 vdc, v gs = 0 vdc, t j = 125 c) i dss ? ? ? ? 1.0 10 adc gate ? body leakage current (v gs = 15 vdc, v ds = 0 vdc) i gss ? ? 100 nadc on characteristics (note 1) gate threshold voltage (c pk 3.0) (note 3) (v ds = v gs , i d = 250 adc) threshold temperature coefficient (negative) v gs(th) 1.0 ? 1.5 4.0 2.0 ? vdc mv/ c static drain ? source on ? resistance (c pk 3.0) (note 3) (v gs = 5.0 vdc, i d = 25 adc) r ds(on) ? 20.9 25 m drain ? source on ? voltage (v gs = 5.0 vdc) (i d = 50 adc) (i d = 25 adc, t j =125 c) v ds(on) ? ? 0.83 ? 1.5 1.3 vdc forward transconductance (v ds = 5.0 vdc, i d = 25 adc) g fs 15 20 ? mhos dynamic characteristics input capacitance (v ds = 25 vdc, v gs = 0 vdc, f = 1.0 mhz) c iss ? 3500 4900 pf output capacitance c oss ? 1550 2170 transfer capacitance c rss ? 550 770 switching characteristics (note 2) turn ? on delay time (v dd = 15 vdc, i d = 50 adc, v gs = 5.0 vdc, r g = 2.3 ) t d(on) ? 22 30 ns rise time t r ? 340 466 turn ? off delay time t d(off) ? 90 117 fall time t f ? 218 300 gate charge (see figure 8) (v ds = 24 vdc, i d = 50 adc, v gs = 5.0 vdc) q t ? 74 100 nc q 1 ? 13.6 ? q 2 ? 44.8 ? q 3 ? 35 ? source ? drain diode characteristics forward on ? voltage (i s = 50 adc, v gs = 0 vdc) (i s = 50 adc, v gs = 0 vdc, t j = 125 c) v sd ? ? 2.39 1.84 3.0 ? vdc reverse recovery time (see figure 15) (i s = 50 adc, v gs = 0 vdc, di s /dt = 100 a/ s) t rr ? 106 ? ns t a ? 58 ? t b ? 48 ? reverse recovery stored charge q rr ? 0.246 ? c internal package inductance internal drain inductance (measured from the drain lead 0.25 from package to center of die) l d ? 3.5 ? nh internal source inductance (measured from the source lead 0.25 from package to source bond pad) l s ? 7.5 ? nh 1. pulse test: pulse width 300 s, duty cycle 2%. 2. switching characteristics are independent of operating junction temperature. 3. reflects typical values. c pk = max limit ? typ 3 x sigma
mtb50p03hdl, mvb50p03hdlt4g http://onsemi.com 3 typical electrical characteristics r ds(on) , drain-to-source resistance (normalized) r ds(on) , drain-to-source resistance (ohms) r ds(on) , drain-to-source resistance (ohms) i d , drain current (amps) t j , junction temperature ( c) v ds , drain-to-source voltage (volts) i dss , leakage (na) i d , drain current (amps) i d , drain current (amps) v ds , drain-to-source voltage (volts) v gs , gate-to-source voltage (volts) i d , drain current (amps) 0 20 40 80 100 60 0 0.4 0.8 1.2 1.6 2.0 0 20 40 80 100 figure 1. on ? region characteristics 1.5 1.9 2.3 2.7 3.5 4.3 figure 2. transfer characteristics 0 20406080100 0.015 0.017 0.021 0.025 0.029 0.015 0.017 0.019 0.021 0.022 figure 3. on ? resistance versus drain current and temperature figure 4. on ? resistance versus drain current and gate voltage -50 0.85 0.95 1.05 1.25 1.35 0 5 10 20 25 30 100 1000 figure 5. on ? resistance variation with temperature figure 6. drain ? to ? source leakage current versus voltage -25 0 25 50 75 100 125 150 60 0.2 0.6 1.0 1.4 1.8 3.9 0.027 0.023 0.019 020406080100 0.020 0.018 0.016 1.15 15 v gs = 10 v 4 v 8 v 100 c 25 c t j = -55 c t j = 25 c 10 v v gs = 5 v v gs = 5 v -55 c v gs = 0 v t j = 125 c 100 c 3 v 3.5 v t j = 25 c 6 v 3.1 v gs = 5 v i d = 25 a t j = 100 c 25 c 2.5 v 5 v 4.5 v v ds 5 v 10
mtb50p03hdl, mvb50p03hdlt4g http://onsemi.com 4 power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( t) are determined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculating rise and fall because drain ? gate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resistive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg ? v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turn ? on and turn ? off delay times, gate current is not constant. the simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg ? v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the off ? state condition when calculating t d(on) and is read at a voltage corresponding to the on ? state when calculating t d(off) . at high switching speeds, parasitic circuit elements complicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. the resistive switching time variation versus gate resistance (figure 9) shows how typical switching performance is af fected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely operated into an inductive load; however, snubbing reduces switching losses. gate-to-source or drain-to-source voltage (volts) c, capacitance (pf) 0 4000 8000 10000 14000 figure 7. capacitance variation 12000 10 0 10 15 20 25 v gs v ds 55 c rss c iss c rss 2000 6000 c oss v gs = 0 v t j = 25 c v ds = 0 v c iss
mtb50p03hdl, mvb50p03hdlt4g http://onsemi.com 5 q t , total gate charge (nc) r g , gate resistance (ohms) t, time (ns) v ds , drain-to-source voltage (volts) v gs , gate-to-source voltage (volts) figure 8. gate ? to ? source and drain ? to ? source voltage versus total charge 110 10 100 1000 v dd = 30 v i d = 50 a v gs = 10 v t j = 25 c t f t d(on) t d(off) figure 9. resistive switching time variation versus gate resistance 010305060 80 20 40 3 6 2 0 1 4 5 30 25 20 15 5 10 0 qt q2 v gs i d = 50 a t j = 25 c v ds q3 q1 70 t r drain ? to ? source diode characteristics the switching characteristics of a mosfet body diode are very important in systems using it as a freewheeling or commutating diode. of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, emi and rfi. system switching losses are largely due to the nature of the body diode itself. the body diode is a minority carrier device, therefore it has a finite reverse recovery time, t rr , due to the storage of minority carrier charge, q rr , as shown in the typical reverse recovery wave form of figure 12. it is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. therefore, one would like a diode with short t rr and low q rr specifications to minimize these losses. the abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. the mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high di/dts. the diode?s negative di/dt during t a is directly controlled by the device clearing the stored charge. however, the positive di/dt during t b is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. therefore, when comparing diodes, the ratio of t b /t a serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. a ratio of 1 is considered ideal and values less than 0.5 are considered snappy. compared to on semiconductor standard cell density low voltage mosfets, high cell density mosfet diodes are faster (shorter t rr ), have less stored charge and a softer reverse recovery characteristic. the softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell mosfet diode without increasing the current ringing or the noise generated. in addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. i s , source current (amps) v sd , source-to-drain voltage (volts) figure 10. diode forward voltage versus current 0 10 30 50 40 20 0.4 0.6 0.8 1.0 1.2 1.4 v gs = 0 v t j = 25 c 1.6 1.8 2.0 2.2 2.4
mtb50p03hdl, mvb50p03hdlt4g http://onsemi.com 6 i s , source current t, time figure 11. reverse recovery time (t rr ) di/dt = 300 a/ s standard cell density high cell density t b t rr t a t rr safe operating area the forward biased safe operating area curves define the maximum simultaneous drain ? to ? source voltage and drain current that a transistor can handle safely when it is forward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, ?transient thermal resistance ? general data and its use.? switching between the off ? state and the on ? state may traverse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded, and that the transition time (t r , t f ) does not exceed 10 s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) ? t c )/(r jc ). a power mosfet designated e ? fet can be safely used in switching circuits with unclamped inductive loads. for reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions dif fering from those specified. although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. the energy rating decreases non ? linearly with an increase of peak current in avalanche and peak junction temperature. although many e ? fets can withstand the stress of drain ? to ? source avalanche at currents up to rated pulsed current (i dm ), the energy rating is specified at rated continuous current (i d ), in accordance with industry custom. the energy rating must be derated for temperature as shown in the accompanying graph (figure 13). maximum energy at currents below rated continuous i d can safely be assumed to equal the values indicated. v ds , drain-to-source voltage (volts) t j , starting junction temperature ( c) e as , single pulse drain-to-source avalanche energy (mj) i d , drain current (amps) figure 12. maximum rated forward biased safe operating area 25 150 50 100 125 75 0 1400 800 600 400 200 1000 figure 13. maximum avalanche energy versus starting junction temperature 0.1 1.0 10 100 1 10 100 1000 100 s 1 ms 10 ms r ds(on) limit thermal limit package limit v gs = 20 v single pulse t c = 25 c i d = 50 a 1200 dc
mtb50p03hdl, mvb50p03hdlt4g http://onsemi.com 7 typical electrical characteristics r(t), effective transient thermal resistance (normalized) t, time (s) figure 14. thermal response 1.0e-05 1.0 0.01 0.1 0.2 0.02 0.01 single pulse r jc (t) = r(t) r jc d curves apply for power pulse train shown read time at t 1 t j(pk) - t c = p (pk) r jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 figure 15. diode reverse recovery waveform di/dt t rr t a t p i s 0.25 i s time i s t b 0 0.5 1 1.5 2.0 2.5 3 25 50 75 100 125 150 t a , ambient temperature ( c) p d , power dissipation (watts) figure 16. d 2 pak power derating curve 0.1 d = 0.5 0.05 r ja = 50 c/w board material = 0.065 mil fr ? 4 mounted on the minimum recommended footprint collector/drain pad size 450 mils x 350 mils 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 1.0e+01 ordering information device package shipping ? mtb50p03hdlg d 2 pak (pb ? free) 50 units / rail MTB50P03HDLT4G d 2 pak (pb ? free) 800 / tape & reel mvb50p03hdlt4g* d 2 pak (pb ? free) 800 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *mvb prefix for automotive and other applications requiring unique site and control change requirements; aec ? q101 qualified and ppap capable.
mtb50p03hdl, mvb50p03hdlt4g http://onsemi.com 8 package dimensions d 2 pak 3 case 418b ? 04 issue k style 2: pin 1. gate 2. drain 3. source 4. drain seating plane s g d ? t ? m 0.13 (0.005) t 23 1 4 3 pl k j h v e c a dim min max min max millimeters inches a 0.340 0.380 8.64 9.65 b 0.380 0.405 9.65 10.29 c 0.160 0.190 4.06 4.83 d 0.020 0.035 0.51 0.89 e 0.045 0.055 1.14 1.40 g 0.100 bsc 2.54 bsc h 0.080 0.110 2.03 2.79 j 0.018 0.025 0.46 0.64 k 0.090 0.110 2.29 2.79 s 0.575 0.625 14.60 15.88 v 0.045 0.055 1.14 1.40 ? b ? m b w w notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. 418b ? 01 thru 418b ? 03 obsolete, new standard 418b ? 04. f 0.310 0.350 7.87 8.89 l 0.052 0.072 1.32 1.83 m 0.280 0.320 7.11 8.13 n 0.197 ref 5.00 ref p 0.079 ref 2.00 ref r 0.039 ref 0.99 ref m l f m l f m l f variable configuration zone r n p u view w ? w view w ? w view w ? w 123 soldering footprint 8.38 5.080 dimensions: millimeters pitch 2x 16.155 1.016 2x 10.49 3.504 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mtb50p03hdl, mvb50p03hdlt4g http://onsemi.com 9 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 mtb50p03hdl/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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